Memory systems may use a partial write command to indicate that at least some of the transferred data is to be masked. The conventional approach to implementing partial writes includes the use of a dedicated data mask pin. For example, a system may include a dedicated data mask pin for each byte lane of data. Thus, a ×16 wide device typically includes two dedicated data mask pins. The data mask pins are typically toggled at the same frequency as the data signals. In many cases, ×4 devices do not support data masking because they are primarily used in servers that have error correction code (ECC) and perform a “read-modify-write” operation.
In addition, the rate at which information is transferred in memory systems continues to increase. These faster transfer rates dictate the use of mechanisms for improved error coverage. Conventional approaches to improving error coverage involve adding pins to the channel. In modern memory systems, the dynamic random memory access (DRAM) channel is pin constrained. Thus, conventional approaches to improving error coverage are not suitable for modern memory systems.